Possible Nanoelectronic Implementation of Neuromorphic Networks

Neuromorphic networks of high connectivity may be implemented using CMOS circuits as cell bodies, nanowires as axons and dendrites, and self-assembled single-molecule latching switches as synapses. The integration scale of such “CrossNet” circuits of acceptable size (~30×30 cm2) may be comparable with that of the mammal’s cerebral cortex (up to 1010 neurons), despite the quasi-2D structure of the artificial networks. At the same time, the speed of information processing and network adaptation may be about 6 orders of magnitude higher than that of the brain, at high but manageable power consumption ~100 W/cm2. We present an overview of the hardware implementation prospects, and possible strategies of CrossNet training. Two suggested Hopfield-mode training methods have been verified on numerical models of the networks. The results are consistent with our estimates of the maximum network capacity with an account for finite interconnect locality.